library verilog;
use verilog.vl_types.all;
entity zl_2346_4 is
    port(
        cin             : in     vl_logic;
        clk             : in     vl_logic;
        s               : in     vl_logic_vector(2 downto 0);
        datain          : in     vl_logic_vector(3 downto 0);
        wt              : in     vl_logic;
        sel             : in     vl_logic;
        en              : in     vl_logic;
        overflow        : out    vl_logic;
        codeout         : out    vl_logic_vector(7 downto 0);
        segsel          : out    vl_logic_vector(7 downto 0)
    );
end zl_2346_4;
